The present invention relates to a semiconductor heterostructure comprising a support substrate with a first in-plane lattice parameter, a buffer structure formed on the support substrate and having on top in a relaxed state a second in-plane lattice parameter, and a multi-layer stack of ungraded layers formed on the buffer structure.
Such heterostructures are used for wafer recycling of a donor wafer after taking off or transferring a useful layer of a semiconductor material and are known from US patent application 2005/0167002 A1. This document describes, for example, a wafer structure such as donor wafer 16 shown in FIG. 7, that includes a silicon support substrate 1 on which a graded SiGe buffer layer 2 with a progressively increasing germanium content is formed, wherein a multi-layer structure of alternating relaxed SiGe layers 3, 3′ and strained silicon layers 4, 8 is formed on the buffer layer 2.
The buffer layer 2 functions to adapt the lattice parameters a1 and a2 between the crystallographic structures of the support substrate 1 and the layers of the multi-layer stack and to reduce thereby the density of defects in the upper multi-layer structure. To perform this function, the buffer layer 2 has at its interface with the support substrate 1 a lattice parameter that is almost identical to the lattice parameter a1 of the support substrate 1, and has at its interface with the multi-layer stack a lattice parameter that is almost identical to the lattice parameter a2 of the layer 3 of the multi-layer stack directly adjacent to the buffer layer 2.
The thickness of the buffer layer 2 is chosen to be between 1 and 3 micrometers for surface concentrations of Ge of less than 30% to obtain a good structural relaxation at the surface, and to confine defects related to the difference in the lattice parameters. The relaxed SiGe layer 3 is formed with a uniform concentration of Ge that is almost identical to the Ge concentration of the buffer layer 2, such as about 20%, and has a typical thickness of about 0.5 to 1 micrometers.
The strained silicon layer 4 which is formed on the relaxed SiGe layer 3 must not exceed a critical thickness for relaxation. For the layer 4 made of strained Si inserted between two layers of relaxed SiGe with a concentration of Ge of about 20%, the critical thickness is of the order of about 20 nanometers.
The multi-layer stack used has a sufficient thickness to form at least two useful layers, such as the strained silicon layers 4, 8, that can be detached and additional material can be removed to planarize exposed surfaces of the useful layers prior to detachment from the donor wafer. In accordance with an example described in US patent application 2005/0167002 A1, the useful layers can be detached from the donor wafer by means of the so-called SMART-CUT® technique including forming of a weakening area in the donor wafer by implantation, bonding the donor wafer with a receiving wafer and subjecting the bonded wafer pair to a thermal and/or mechanical treatment, or a treatment with any other type of energy input, to detach it at the weakening area.
Although the principle of the process described in the document US patent application 2005/0167002 A1 is well suited for layer detachment and wafer recycling, it may require multiple polishing steps to provide sufficient low roughness of top layer. Indeed, it has been shown that, with a reduced number of polishing steps, the roughness of the surface 9 of the top layer 8 of the donor wafer 16 is in a region between 7 and 10 Å RMS on a 2×2 μm scan so that the known donor wafer structures are not suitable for direct wafer bonding which is important for the SMART-CUT® process. Accordingly, there is a need for semiconductor hetero-structures of the above-mentioned type that have lower surface roughness values.